This model supports ESP32s with at least 4MB of flash.
Today ESP32s come in multiple flavors. This model supports the classical ESP32 chips running a dual-core on the Xtensa LX6 architecture:
They are embedded in the following official modules:
And most likely any other module with the above mentioned chips, with a minimum of 4 MB flash.
That also means that it doesn't support the following:
- ESP32-S2 (Single-core / Xtensa LX7)
- ESP32-C3 (Single-core / RISC-V)
- ESP32-S3 (Xtensa LX7)
- ESP32-C6 (Single-core / RISC-V)
esp32-4mb model supports a number of model-specific parameters, to control core peripherals.
In case the core peripherals are behind a secondary power circuit, the
pwr option can be used to turn it on.
|model.pwr||Pin number for the pwr line. Lazily driven active for the duration a core peripheral is needed.|
|model.pwr.mode||The mode of the |
Cellular can be enabled using the follow model parameters. When enabled, the Cellular subsystem will use the devices Cellular connectivity settings that can be configured in the Console at runtime.
|model.cellular.enabled||If set to ||Required|
|model.cellular.sara_r4||If set to |
|model.cellular.sara_r5||If set to |
|model.cellular.pwr||Pin number for the power-on line. This pin is periodically driven active to request the Cellular module to turn on.||Required|
|model.cellular.pwr.mode||The mode of the |
|model.cellular.reset||Pin number for the power-on line. This pin is occasionally driven active if the Cellular module fails to turn on.|
|model.cellular.reset.mode||The mode of the |
|model.cellular.tx||Pin number for the UART TX line.||Required|
|model.cellular.rx||Pin number for the UART RX line.||Required|
|model.cellular.rts||Pin number for the UART RTS line.|
|model.cellular.cts||Pin number for the UART CTS line.|